1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to charge trapping memory technology adaptable for high speed erase and program operations and suitable for use as embedded memory in large scale integrated circuits.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate. Charge trapping memory cells use dielectric charge trapping material that does not cause cell-to-cell interference like that encountered with floating gate technology, and is expected to be applied for higher density flash memory.
The typical charge trapping memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a stack of dielectric material including a tunneling dielectric layer, the charge storage layer, and a blocking dielectric layer. According to the early conventional designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunneling dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed a silicon oxide (O), and the gate comprises polysilicon (S). The SONOS device is programmed by electron tunneling using one of a number of well-known biasing technologies, and erased by hole tunneling or electron de-trapping. In order to achieve practical operational speeds for the erase operation, the tunneling dielectric layer must be quite thin (less than 30 Å). However at that thickness, the endurance and charge retention characteristics of the memory cell are poor relative to traditional floating gate technology. Also, with relatively thick tunneling dielectric layers, the electric field required for the erase operation also causes electron injection from the gate through the blocking dielectric layer. This electron injection causes an erase saturation condition in which the charge level in the charge trapping device converges on an equilibrium level. See, U.S. Pat. No. 7,075,828, entitled “Operation Scheme with Charge Balancing Erase for Charge Trapping Non-Volatile Memory”, invented by Lue et al. However, if the erase saturation level is too high, the cell cannot be erased at all, or the threshold margin between the programmed and erased states becomes too small for many applications.
One focus of investigation for charge trapping memory cells has been on NAND style architectures. See, for example, Shin et al., “A Highly Reliable SONOS-type NAND Flash Memory Cell with Al2O3 or Top Oxide,” IEDM, 2003 (MANOS); and Shin et al., “A Novel NAND-type MONOS Memory using 63 nm Process Technology for a Multi-Gigabit Flash EEPROMs”, IEEE 2005.
In a NAND style architecture, the memory cells are arranged in series so that current used for reading data passes through a string of memory cells which limits the amount of current and the speed at which the read operation can be accomplished.
An alternative architecture used in floating gate memory devices that are designed for higher speed read applications is known as the NOR architecture. In a NOR architecture, the memory cells are arranged in parallel between local bit lines and reference lines. In this way, the current during a read operation can be relatively high. However, any leakage current from the cells along a given bit line can interfere with the ability to successfully read the data. Thus, some NOR architecture devices are arranged in a two-transistor (2T) cell structure, where each memory cell includes an access transistor and a data storage transistor connected in series. The access transistor can be used to isolate the data storage transistor from the bit line and prevent leakage from interfering with the reading of other cells.
An example 2T NOR architecture is shown in FIG. 1, which is similar to that described in Tao, et al., “A Quantitative Study of Endurance Characteristics and Its Temperature Dependence of Embedded Flash Memories With 2T-FNFN NOR Device Architecture,” IEEE TRANSACTIONS ON DEVICE MATERIALS RELIABILITY, Volume 7, No. 2, June, 2007. According to this prior art technology, an array includes a plurality of access gate word lines AG1, AG2, . . . , and a plurality of memory gate word lines MG1, MG2, . . . , arranged orthogonally relative to a plurality of bit lines BL1, BL1,  . . . A unit memory cell includes an access transistor 10 and a floating gate memory transistor 11. An access gate word line (e.g. AG2) is coupled to the gate of the access transistors in a row, and a memory gate word line (e.g., MG2) is coupled to the control gate of the floating gate transistors along the row. The source of the access transistor 10 is coupled to the reference line SL. The drain of the floating gate transistor 11 is coupled to the bit line (e.g. BL1). The access transistor 10 and a floating gate transistor 11 share a terminal between them, acting as the source of the floating gate transistor 11 in the drain of the access transistor 10. As can be seen, in this architecture two unit cells share a bit line contact 12 and are arranged in mirror image on either side of the shared bit line contact 12. The source line SL can be arranged generally in parallel with the access gate word lines as shown.
FIG. 2 illustrates the basic two transistor cell for floating gate implementations. The structure is formed on the semiconductor body 20, which is typically an isolated p-type well on a chip. The memory transistor in the cell includes a control gate 21 (coupled to a memory gate word line), and a floating gate 22 which are made using polysilicon in separate deposition and patterning steps. The floating gate 22 is separated from the semiconductor body 20 by a tunnel dielectric 23 which is typically a silicon dioxide layer. The floating gate is isolated from the control gate 21 by an inter-poly-dielectric 24, which is typically implemented using an oxide/nitride/oxide structure designed to block charge leakage caused by tunneling between the control gate and the floating gate. The access transistor includes an access gate 25 and a gate dielectric layer 26 over the semiconductor body 20. A drain terminal 27 is implemented using an n+doped region, and coupled to a bit line as shown in FIG. 1. Source region 29 implemented using an n+doped region on the opposite side of the access transistor is coupled to the source line SL of the array as shown in FIG. 1. A terminal 28 implemented using an n+ doped region between memory transistor and access transistor acts as the source for the memory transistor and as the drain for the access transistor. Problems associated with the use of floating gate memory devices, including the need to use, and associated costs of, two separate polysilicon deposition steps. Also, problems arise as the size of the devices shrinks with interference between adjacent cells. These issues have prevented its widespread use for embedded memory on large system-on-a-chip, high density devices.
A similar 2T NOR architecture is described in U.S. Pat. No. 5,319,229 by Shimoji et al Shimoji et al. proposes the use of a charge trapping memory cell, which is programmed and erased at relatively low voltages, in combination with an access transistor. The Shimoji et al. cell, because of its low voltage operation during programming and erasing, is likely to suffer problems with disturbance of the charge stored in the memory transistor even at low voltages used for driving the access transistors.
The present inventor has been involved in the development a charge trapping memory using bandgap engineered charge trapping technology, referred to as BE-SONOS. A variety of embodiments of BE-SONOS memory cells can be seen in U.S. Pat. No. 7,426,140 B2 by Lue, and in U.S. Patent Application Publication No. US2007/0029625 by Lue et al. BE-SONOS is characterized by the ability to block charge tunneling at relatively low electric fields, while enabling very efficient tunneling at moderately high electric fields. BE-SONOS also has very good endurance and reliability characteristics.
It is desirable to provide for an embedded memory usable in large-scale system-on-a-chip devices, operable at relatively low voltage, which allows for high speed read access, which has a relatively small footprint on the device, and which is simple to manufacture.